Design a CMOS output stage based on the circuit of Fig 5 31 to deliver plusmn 1 V before clipping at V o with R L 1 k Icirc copy and V DD V SS 2 5 V Use 10 micro A bias current in M 3 and 100 micro A idling current in M 1 and M 2 Set (W L) 3 50 1 and (W L) 6 25 1 Specify the W L for M 1 M 6 that mi...

008 2 fn 650 mV 2 fp 750 mV Table 23 K n 127 AV K P 58 AV V tn 07 V V ...

Design a CMOS output stage based on the circuit of Fig. 5.31 to deliver ±1 V before

Question:

Design a CMOS output stage based on the circuit of Fig. 5.31 to deliver ±1 V before clipping at V_owith R_L= 1 kÎ© and V_DD= V_SS= 2.5 V. Use 10 µA bias current in M₃and 100 µA idling current in M₁and M₂. Set (W/L)₃= 50/1 and (W/L)₆= 25/1. Specify the W/L for M₁-M₆that minimizes the total chip area. Use the transistor parameters in Table 2.3 except assume that L_eff= L_drwnfor simplicity. The minimum channel length is 1 µm. Assume the body of each n-channel transistor is connected to ˆ’V_SS, and the body of each p-channel transistor is connected to V_DD. Use SPICE to verify your design by plotting the V_oversus V_icharacteristic.

Figure 5.31:

VDp BIAS Мз M4 V. RL M2 M5. M6 V; -Vss