For the output stage of Fig. 5.18, assume that V CC = 15 V and for all

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For the output stage of Fig. 5.18, assume that VCC= 15 V and for all devices VCE(sat)= 0.2 V, VBE(on)= 0.7 V, and βF= 50.

Fig. 5.18:

+Vcc R4 20 k2 R1 02 Q3 +o V; -Vcc

(a) Calculate the maximum positive and negative limits of Vo for RL = 10 kΩ and RL = 2 kΩ.

(b) Calculate the maximum average power that can be delivered to RL before clipping occurs for RL = 10 kΩ and RL = 2 kΩ. Calculate the corresponding circuit efficiency (for the output devices only) and the average power dissipated per output device. Neglect crossover distortion and assume sinusoidal signals. 

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Analysis and Design of Analog Integrated Circuits

ISBN: 978-0470245996

5th edition

Authors: Paul R. Gray, ‎ Paul J. Hurst Stephen H. Lewis, ‎ Robert G. Meyer

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