A computer with a separate data cache has a writeback cache memory. Cache line size is 64
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A computer with a separate data cache has a writeback cache memory. Cache line size is 64 bytes. Read access accounts for 80% of memory traffic. The processor, memory, and data buses are all 64-bits wide. Main memory latency (first access) is 20 cycles, and successive accesses take two cycles. The cache hit rate is 96%.
Calculate the cost of a cache miss.
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Related Book For
Computer Organization And Architecture Themes And Variations
ISBN: 9781111987046
1st Edition
Authors: Alan Clements
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