Assuming there are no stalls and that 60% of all conditional branches are taken, in what percentage of clock cycles does the branch adder in the EX stage generate a value that is actually used?

Problems in this exercise assume that instructions executed by a pipelined processor are broken down as follows:

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a. b. ADD 40% 60% BEQ 30% 10% LW 25% 20% SW 5% 10%