If an overflow exception occurs once for every 100,000 instructions executed, what is the overall speedup if we move overflow checking into the MEM stage? Assume that this change reduces EX latency by 30ns and that the IPC achieved by the pipelined processor is 1 when there are no exceptions.

The remaining three problems in this exercise assume that pipeline stages have the following latencies:

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a. b. IF 220ps 175ps ID 150ps 150ps EX 250ps 200ps MEM 200ps 175ps WB 200ps 140ps