Repeat 4.27.1, but this time assume that the instruction in the delay slot also causes a hardware error exception when it is in MEM stage.

Exercise 4.27.1

Assume that this branch is correctly predicted as taken, but then the instruction at “Label” is an undefined instruction. Describe what is done in each pipeline stage for each cycle, starting with the cycle in which the branch is
decoded up to the cycle in which the first instruction of the exception handler is fetched.

This exercise examines how exception handling interacts with branch and load/ store instructions. Problems in this exercise refer to the following branch instruction and the corresponding delay slot instruction:

Transcribed Image Text:

a. b. BEQ R5, R4, Label SLT R5, R15, R4 BEQ LW R1, RO, Label R1,0 (R1) Branch and Delay Slot