Repeat 4.6.2, but this time we need to support only conditional PC-relative branches. Problem 4.6.2 Consider a

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Repeat 4.6.2, but this time we need to support only conditional PC-relative branches.

Problem 4.6.2

Consider a datapath similar to the one in Figure 4.11, but for a processor that only has one type of instruction: unconditional PC-relative branch. What would the cycle time be for this datapath?

Figure 4.11PC Read address Add Instruction Instruction memory Read register 1 Read register 2 Write register Write data


Problems in this exercise assume that logic blocks needed to implement a processor’s datapath have the following latencies:I-Mem Add Mux ALU 70ps 20ps 90ps 200ps 50ps 250ps a. 200ps b. 750ps Regs D-Mem Sign-Extend Shift-Left-2 90ps

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Computer Organization And Design The Hardware Software Interface

ISBN: 9780123747501

4th Revised Edition

Authors: David A. Patterson, John L. Hennessy

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