What are the best-case and worst-case numbers of cache misses needed to execute the listed read/write instructions?

Cache coherence concerns the views of multiple processors on a given cache block. The following table shows two processors and their read/write operations on two different words of a cache block X (initially X[0] = X[1] = 0).

Transcribed Image Text:

a. b. X[0] ++ X[1] X[0] =10; X[1] = P1 3; = 3; X[0] X[0] = = P2 5; X[1] +=2; 5; X[1] +=2;