What is the optimal block size for a miss latency of 20B cycles? Cache block size (B)
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What is the optimal block size for a miss latency of 20×B cycles?
Cache block size (B) can affect both miss rate and miss latency. Assuming a 1-CPI machine with an average of 1.35 references (both instruction and data) per instruction, help find the optimal block size given the following miss rates for various block sizes.
Transcribed Image Text:
a. b. 8 4% 8% 16 3% 7% 32 2% 6% 64 1.5% 5% 128 1% 4%
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To find the optimal block size given a miss latency of 20B cycles we can calculate the Average Memor...View the full answer
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Related Book For
Computer Organization And Design The Hardware Software Interface
ISBN: 9780123747501
4th Revised Edition
Authors: David A. Patterson, John L. Hennessy
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