Which pipeline stages can you slow down and by how much, without affecting the clock cycle time?

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Which pipeline stages can you slow down and by how much, without affecting the clock cycle time?


Problems in this exercise assume that, during an execution of the program, processor cycles are spent in the following way. A cycle is "spent" on an instruction if the processor completes that type of instruction in that cycle; a cycle is "spent" on a stall if the processor could not complete an instruction in that cycle because of a stall.a. b. ADD 25% 25% BEQ 20% 10% LW 20% 25% SW 10% 20% Control Stalls 10% 10% Data Stalls 15% 10%

Problems in this exercise also assume that individual pipeline stages have the following latency and energy consumption. The stage expends this energy in order to do its work within the given latency. Note that no energy is spent in the MEM stage during a cycle in which there is no memory access. Similarly, no energy is spent in the WB stage in a cycle in which there is no register write. In several of the following problems, we make assumptions about how energy consumption changes if a stage performs its work slower or faster than this.IF a. 250ps/100pJ b. 200ps/75pJ ID 350ps/45pJ 170ps/45pJ EX 150ps/50pJ 220ps/100pJ MEM 300ps/150pJ

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Computer Organization And Design The Hardware Software Interface

ISBN: 9780123747501

4th Revised Edition

Authors: David A. Patterson, John L. Hennessy

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