Insert an exclusive-OR gate between MUX 2 and the input logic of Fig. 7-8. One input to the gate comes from the test output of the multiplexer. The other input to the gate comes from a bit labeled P (for polarity) in the microinstruction from control memory. The output of the gate goes to the input T of the input logic. What does the polarity control P accomplish?

Fig. 7-8

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1152 317 Input logic MUX2 Select External (MAP) Test Microops 3210 S₁ MUX 1 So Clock>> CAR Control memory BR Incrementer AD SBR Load