Let n be the number of bits of the mantissa in a binary floating-point number. When the mantissas are aligned during the addition or subtraction, the exponent difference may be greater than n - 1. If this occurs, the mantissa with the smaller exponent is shifted entirely out of the register. Modify the mantissa alignment in Fig. 10-15 by including a sequence counter SC that counts the number of shifts. If the number of shifts is greater than n - 1, the larger number is then used to determine the result.

Fig. 10-15

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Check for zeros Add or subtract = 0 BR Add #0 AC BR op = 0 Sub A₂ + A₂ AC = 0 A+ A + 1 A₂ + A₂ shl A ata-l #0 shr A a+a+1 #0 = 0 a b AC+0 shr B b+b+1 Add A, B, EA + A+B = 0 E shr A A₁ + E a+a+l Align mantissas Mantissa addition or subtraction Normalization