The bus system of Fig. 8-2 has the following propagation delay times: 30 ns for the signals to propagate through the multiplexers, 80 ns to perform the ADD operation in the ALU, 20 ns delay in the destination decoder, and 10 ns to clock the data into the destination register. What is the minimum cycle time that can be used for the clock?

Fig. 8-2

Transcribed Image Text:

R1 R2 R3 R4 R5 R6 R7 Load (7 lines) Clock 3x8 decoder SELD SELA OPR | | | | | MUX A bus Arithmetic logic unit (ALU) Output (a) Block diagram 3 3 3 SELA SELB SELD (b) Control word 5 OPR MUX 8 bus Input SELB