The outputs of four registers, R0, R1, R2, and R3, are connected through 4-to-1-line multiplexers to the inputs of a fifth register, R5. Each register is eight bits long. The required transfers are dictated by four timing variables To through T, as follows: 

To: R5 RO 

T: R5 R1 

T: R5 R2 

T: R5-R3

The timing variables are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the other three are equal to 0. Draw a block diagram showing the hardware implementation of the register transfers. Include the connections necessary from the four timing variables to the selection inputs of the multiplexers and to the load input of register R5.