Register ID dstM indicates the destination register for write port M, where valM, the value read from memory, is stored. This is shown in Figures 4.18 to 4.21 as the second step in the write-back stage. Write HCL code for dstM.

Figures 4.18

Figures 4.21

Transcribed Image Text:

Stage Fetch Decode Execute Memory Write back PC update OPq rA, rB icode: ifun + M₁ [PC] rA:rB M₁ [PC + 1] valp PC+2 valA - R[RA] valB+ R[RB] valEvalB OP valA Set CC R[TB] <-valE PC ← valP rrmovq rA, rB icode:ifun ← M₁[PC] rA:rB ← M₁[PC + 1] valp PC+2 valA - R[RA] valE 0+valA R[RB] valE PC- valp irmovq V, rB icode:ifun - M₁[PC] M₁ [PC + 1] Mg[PC + 2] PC+10 rA:rB ← valc ← valp ← valE 0+valC R[RB] valE PC - valp