Repeat Problem 6.13 for memory address 0x0A31. A. Address format (1 bit per box): B. Memory reference:

Question:

Repeat Problem 6.13 for memory address 0x0A31.

A. Address format (1 bit per box):

12 11 10 9 8 7 6 5 4 3 2 1 0

B. Memory reference:

Parameter Cache block offset (CO) Cache set index (CI) Cache tag (CT) Cache hit? (Y/N) Cache byte returned

Problem 6.13

Suppose a program running on the machine in Problem 6.12 references the 1-byte word at address 0x0D53. Indicate the cache entry accessed and the cache byte value returned in hexadecimal notation. Indicate whether a cache miss occurs. If there is a cache miss, enter “—” for “Cache byte returned.”

Address format (1 bit per box):

12 11 10 9 8 7 6 5 4 3 2 1 0

Memory reference:

Parameter Cache block offset (CO) Cache set index (CI) Cache tag (CT) Cache hit? (Y/N) Cache byte returned

Problem 6.12

The problems that follow will help reinforce your understanding of how caches work. Assume the following:

. The memory is byte addressable.

. Memory accesses are to 1-byte words (not to 4-byte words).

. Addresses are 13 bits wide.

. The cache is two-way set associative (E = 2), with a 4-byte block size (B = 4) and eight sets (S = 8).

The contents of the cache are as follows, with all numbers given in hexadecimal notation.

Set index 0 1234567 Line 0 Tag Valid Byte 0 Byte 1 Byte 2 Byte 3 09 1 86 30 3F 10 45 1 60 4F E0 23 EB 0 06 C7

The following figure shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following:

CO. The cache block offset 

CI. The cache set index

CT. The cache tag

12 11 10 9 8 7 6 5 4 3 2 1 0

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Related Book For  book-img-for-question

Computer Systems A Programmers Perspective

ISBN: 9781292101767

3rd Global Edition

Authors: Randal E. Bryant, David R. O'Hallaron

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