Is it possible to assign logic levels so that a device with the transfer characteristics shown in
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Is it possible to assign logic levels so that a device with the transfer characteristics shown in Figure 1.46 would serve as a buffer? If so, what are the input and output low and high levels (VIL,VOL,VIH, and VOH) and noise margins (NML and NMH)? If not, explain why not.
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Vout 5- 4 - 3- 2- 1 Vin 0 1 3 4 5 Figure 1.46 DC transfer characteristics
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Related Book For
Digital Design and Computer Architecture
ISBN: 978-0123944245
2nd edition
Authors: David Harris, Sarah Harris
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