Repeat Exercise 4.48 if the module codel(input logic clk, a, b, c. output logic y): logic x:
Question:
Repeat Exercise 4.48 if the <= is replaced by = in every assignment.
Data from problem 48
Consider the following two SystemVerilog modules. Do they have the same function? Sketch the hardware each one implies.
Transcribed Image Text:
module codel(input logic clk, a, b, c. output logic y): logic x: always_ff @(posedge clk) begin x (= a & b; y <= x | c; end endmodule module code2 (input logic a, b. c. clk, output logic y): logic x; always_ff @(posedge clk) begin y <= x | c: x (= a & b: end endmodule
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Related Book For
Digital Design and Computer Architecture
ISBN: 978-0123944245
2nd edition
Authors: David Harris, Sarah Harris
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