Sketch a schematic of the circuit described by the following HDL code. Simplify the schematic so that it shows a minimum number of gates.

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SystemVerilog VHDL module exerctsel (input 1ogt ca, b. c. output l ogi c y. z); 1ibrary IEEE; use IEEE.STD LOGIC_1164.all: assign y = a & b &c|a &b & -c | a & -b & c: assi gn z = a & b| -a & -b: entity exerci sel is port (a. b. c: in y. z: STD LOGIC; out STD LOGI C): endmodule end: architecture synth of exercisel is begin y <= (a and b and c) or (a and band not c) or (a and not b and c): z (= (a and b) or (not a and not b); end: