Use a synthesis tool to synthesize the Fibonacci circuits you wrote in Exercises 7.1–7.3. Draw the resulting logic diagram for each synthesis outputs circuit. Compare and contrast the output circuits from each design entity. 

Data in Exercises 7.1

Write a VHDL description for a circuit that accepts a four-bit input and outputs true if the input is a Fibonacci number (0, 1, 2, 3, 5, 8, or 13). Your implementation must be done via a case statement.