a) Perform the floating point addition. b) Draw an SM chart for a floating-point adder that adds

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a) Perform the floating point addition.
b) Draw an SM chart for a floating-point adder that adds F1 x 2E1 and F2 x 2E2. Assume that the fractions are initially normalized (or zero) and the final result should be normalized (or zero). A zero fraction should have an exponent of -8. Set an exponent overflow flag (EV) if the final answer has an exponent overflow. Each number to be added consists of a 4-bit fraction and a 4-bit exponent, with negative numbers represented in 2’s complement. Assume that all registers (F1, E1, F2, and E2) can be loaded in one clock time when a start signal (St) is received. If E1 > E2, the control signal GT = 1, and if E1 < E2, the control signal LT = 1. Define all other control signals used. Include the special case where |E1 - E2| > 3.

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Digital Systems Design Using Verilog

ISBN: 978-1285051079

1st edition

Authors: Charles Roth, Lizy K. John, Byeong Kil Lee

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