Design a multiplier that will multiply two 16-bit signed binary integers to give a 32-bit product. Negative numbers should be represented in 2’s complement form. Use the following method: First complement the multiplier and multiplicand if they are negative, multiply the positive numbers, and then complement the product if necessary. Design the multiplier so that after the registers have been loaded, the multiplication can be completed in 16 clocks.
(a) Draw a block diagram of the multiplier. Use a 4-bit counter to count the number of shifts. (The counter will output a signal K = 1 when it is in state 15.)
Define all condition and control signals used on your diagram. 

(b) Draw a state diagram for the multiplier control using a minimum number of states (five states). When the multiplication is complete, the control circuit should output a done signal and then wait for ST = 0 before returning to state S₀.
(c) Write a Verilog behavioral description of the multiplier without using control signals (e.g,. see Figure 4-35) and test it.
(d) Write a Verilog behavioral description using control signals (e.g., see Figure 4-40) and test it.