Draw the circuit represented by the following Verilog process: always @(clk,clr) begin if(clr == 1'b1) Q
Question:
Draw the circuit represented by the following Verilog process:
always @(clk,clr)
begin
if(clr == 1'b1)
Q <= 1'b0;
else if(clk == 1'b0 && CE == 1'b1)
begin
if(C == 1'b0)
Q <= A & B;
else
Q <= A | B;
end
end
Why is clr on the sensitivity list whereas C is not?
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Clr is asynchronous w...View the full answer
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Related Book For
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
Question Posted:
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