What is wrong with the following code for a half adder that must add if add signal
Question:
What is wrong with the following code for a half adder that must add if add signal equals 1?
always @(x)
begin
if (add == 1)
begin
sum = x ^ y;
carry = x & y;
end
else
begin
sum = 0;
carry = 0;
end
end
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Related Book For
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
Question Posted:
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