Add the necessary logic circuitry to Figure 6-10 to accommodate the transfer of data from memory into the A register. The data values from memory are to enter the A register through its D inputs on the PGT of the first TRANSFER pulse; the data from the sum outputs of the FAs will be loaded into A on the PGT of the second TRANSFER. In other words, a LOAD pulse followed by two TRANSFER pulses is required to perform the complete sequence of loading the B register from memory, loading the A register from memory, and then transferring their sum into the A register.

Figure 6-10

Transcribed Image Text:

LOAD> C4 CLEAR> TRANSFER> CLKD FA D >CLK B₂ A₂ CLR CLEAR LOAD TRANSFER I I 4 1 T CLK D DCLK 12 FA CLR D B₂ A₂ T 1 13 S₁ CLK 1₂ FA D >CLK CLR (h) D B₂ 100 A₁ Accumulator outputs (a) 1 1 5 Sor CLK D FA D >CLK CLR Bo Ao B register -Co 4-bit adder A register