Assume that the gates in Figure 4-41 are all CMOS. When the technician tests the circuit, he finds that it operates correctly except for the following conditions:

1. A = 1, B = 0, C = 0 

2. A = 0, B = 1, C = 1 

For these conditions, the logic probe indicates indeterminate levels at Z2-6, Z2-11, and Z2-8. What do you think is the probable fault in the circuit? Explain your reasoning.

Figure 4-41

Transcribed Image Text:

A B 2 +5 V 14 Z1 X 5 13 12 Z2 +5 V 14 Z2 61 10 11 ICs are TTL Z1: 74LS86 Z2: 74LS00 9 Z2 Pin Z1-1 Z1-2 Z1-3 Z2-4 Z2-5 8 Z2-6,10 Z2-13 Z2-12 Z2-9,11 Z2-8 Condition LOW LOW HIGH LOW HIGH HIGH HIGH HIGH LOW HIGH