We pointed out that I/O buses do not need separate address lines. Construct a timing diagram similar to Figure 7.11 that describes the handshake between an I/O controller and a disk controller for a write operation.

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Time to to t₁ 1₂ 13-17 tg Request Address Write/read Ready Data (Bus) clock Salient bus signal Assert write Assert address Assert request Assert ready Data lines Lower ready 13 T I T X Meaning Bus is needed for writing (not reading) Indicates where bytes will be written Request write to address on address lines FIGURE 7.11 A Bus Timing Diagram 110 Acknowledges write request, bytes placed on data lines Write data (requires several cycles) Release bus