Write Verilog code for the FSM described in Problem 6.9. Data From Problem 6.9. A sequential circuit
Question:
Write Verilog code for the FSM described in Problem 6.9.
Data From Problem 6.9.
A sequential circuit has two inputs, w1 and w2, and an output, z. Its function is to compare the input sequences on the two inputs. If w1 = w2 during any four consecutive clock cycles, the circuit produces z = 1; otherwise, z = 0. For example
w1 : 0110111000110
w2 : 1110101000111
z : 0000100001110
Derive a suitable circuit.
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a The suitable circuit is as follows i The truth table is as follows w1 w2 z 1 0 0 0 1 1 0 1 ...View the full answer
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Related Book For 
Fundamentals Of Digital Logic With Verilog Design
ISBN: 9780073380544
3rd Edition
Authors: Stephen Brown, Zvonko Vranesic
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