Assume that the transfers with strobing shown in Figure 11-7 are between a CPU on the left and an I/O interface on the right. There is an address coming from the CPU for each of the transfers, both of which are initiated by the CPU.

(a) Draw block diagrams showing the interconnections for the transfers.

(b) Draw the timing diagrams for the two transfers, assuming that the address must be applied some time before the strobe becomes 1 and removed some time after the strobe becomes 0.

 Figure 11-7

Transcribed Image Text:

Destination unit Data bus Strobe- Source unit Data bus Strobe Data bus Strobe (a) Destination-initiated transfer Data bus Strobe Source unit (b) Source-initiated transfer Destination unit