Design a digital system with three 16-bit registers AR, BR, and CR and 16-
bit data input IN to perform the following operations, assuming a 2s complement representation and ignoring overlow:

(a) Transfer two 16-bit signed numbers to AR and BR on successive clock cycles after a go signal G becomes 1.

(b) If the number in AR is positive but nonzero, multiply the contents of BR by two and transfer the result to register CR.

(c) If the number in AR is negative, multiply the contents of AR by two and transfer the result to register CR.

(d) If the number in AR is zero, reset register CR to 0.

All iles referred to in the remaining problems are available in ASCII form for simulation and editing on the Companion Website for the text. A VHDL or Verilog compiler/simulator is necessary for the problems or portions of problems requesting simulation. Descriptions can still be written, however, for many problems without using compilation or simulation.