The cache in Figure 12-9 is to be redesigned to use write-back with write allocate rather than write-through. Respond to the following requests, making sure to deal with all of the address and data issues involved in the write-back operation.

(a) Draw the new block diagram.

(b) Explain the sequence of actions you propose for a write miss and for a read miss.

Figure 12-9

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CPU- Hit/miss Read Cache Write control 134 Index Valid bits 1 Valid bits 0 LIS Read CPU data bus 31 Tag Tag 17 16 Index (a) Memory address Address bus Cache data bus Match logic Match logic Match 1 Match On 4 3 2 1 0 Word Byte (b) Cache diagram 32 Tag Tag Data Data memory 1 memory 0 memory 1 memory 0. ZATATA 128 32 128 2 32 Word Main memory Write Hit/miss - Main memory 4-to-1 MUX Read on miss