(a) Assume the inverters have a delay of 1 ns and the other gates have a delay...
Fantastic news! We've Found the answer you've been seeking!
Question:
(a) Assume the inverters have a delay of 1 ns and the other gates have a delay of 2 ns. Initially A = B = C = 0 and D = 1; C changes to 1 at time 2 ns. Draw a timing diagram showing the glitch corresponding to the hazard.
(b) Modify the circuit so that it is hazard free. (Leave the circuit as a two-level, OR- AND circuit.)
Related Book For
Systems analysis and design
ISBN: 978-0136089162
8th Edition
Authors: kenneth e. kendall, julie e. kendall
Posted Date: