1. A sequential circuit has two JK flip-flops A and B, two inputs x and y,...

  

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1. A sequential circuit has two JK flip-flops A and B, two inputs x and y, and one output Z. The flip-flop input equations and circuit output equation are: (a) Draw the logic diagram of the circuit. (b) Derive the state table. (c) Derive the state diagram. 000 JA = Bx + B'y' JB = A'x 111 2. Draw a state diagram of a Mealy circuit having a single input x, and a single output y, such that y is 1 if the total number of the 1's received is a multiple of 3. 3. Considering the following state diagram for a 3-bits counter: 001 z = x'y' (A + B) 110 010 KA = B'xy' Kg = A + xy' 101 011 100 (a) Design the circuit using T flip-flops. (b) Using the Verilog modules we wrote in the sequential circuit's tutorial session, write a Verilog module for a T flip-flop with asynchronous reset. (c) Write a Verilog module and a test-bench for the counter circuit. 1. A sequential circuit has two JK flip-flops A and B, two inputs x and y, and one output Z. The flip-flop input equations and circuit output equation are: (a) Draw the logic diagram of the circuit. (b) Derive the state table. (c) Derive the state diagram. 000 JA = Bx + B'y' JB = A'x 111 2. Draw a state diagram of a Mealy circuit having a single input x, and a single output y, such that y is 1 if the total number of the 1's received is a multiple of 3. 3. Considering the following state diagram for a 3-bits counter: 001 z = x'y' (A + B) 110 010 KA = B'xy' Kg = A + xy' 101 011 100 (a) Design the circuit using T flip-flops. (b) Using the Verilog modules we wrote in the sequential circuit's tutorial session, write a Verilog module for a T flip-flop with asynchronous reset. (c) Write a Verilog module and a test-bench for the counter circuit.

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A nice set of questions 1 Sequential Circuit a Logic Diagram The logic diagram can be drawn by using ... View the full answer