1. An arithmetic logic unit (ALU) is the center of a central processing unit (CPU). It...
Fantastic news! We've Found the answer you've been seeking!
Question:
Transcribed Image Text:
1. An arithmetic logic unit (ALU) is the center of a central processing unit (CPU). It performers a set of arithmetic and logical micro operations on two input buses at every rising edge of CLK input signal. An active high RST input is used to synchronously reset the output signal Y to logical zeros. The output Y must be available at every rising edge of CLK and the latencies for all functions is 1 cycle. Inputs of ALU: CLK, RST, 8-bit unsigned A, 8-bit unsigned B, 4-bit unsigned SEL Output of ALU: 8-bit unsigned Y Function table of ALU is given below: Function SEL Operation Number ] 2 3 4 5 6 7 8 9 10 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 YA Y<=A+B Y<=A+Bbar YA and B Y<A or B Y<=Axor B Y< Abar Ys=shl A Y<=shr A Y<=0 Go to OpenLane folder Sed -/Openlane Ssudo make mount. Now Openlane docker is started S/flow.tel -design alu-init_design_contig package require openlane 0.9 %prep - design alu %run synthesis Sru_lourplan %run placement Srun_cts The whole functions can be implemented using a single case statement even if it is not an optimal way of doing it. You are free to implement them in your way. You can ignore the carry out in addition operations. run routing Srun magic run_magic_spice_export run magic dre %run lvs run antenna_check. A. (35 Points) Implement the given ALU entity in VHDL language. Provide your VHDL code. (35 Points) Implement the given ALU module in Verilog language. Provide your ende. C. (30 Points) Implement the given ALU using OpenLane Design Flow. Hint: Install OpenLane and Magic tools into your Linux machine as described in the class. Create required design files (alu.v, config.tel and sky130A_sky130_fd_sc_hd_config.tcl) and run the following commands those are also described in the class. Function This command creates an alu folder under /designs folder Copy and modify the design files to this folder same as other example designs flow.tel-interactive Transfer A Addition A plus l's complement of B Logical AND Logical OR Logical XOR Complement A Shift left A Shift right A Transfer 0's Go to this folder Sad -/Openlame/designs/counter/runs/..../results/finishing Run magic Smagic -T sky 130A lef read../../tmp/merged lef def read alu.gds & After completion of flow without any error you can run mugic to see GDSII of your design. Open a new terminal and run the following commands. Make sure nor error is generated throughout the flow. set env(IP SIZING) "absolute" set enviDIE AREA) "0 0 100.0 100.0" In the first part of design, let's make the DIE_AREA is absolute and 100 mx100um and set clock frequency to 200MHz.. You can do it hy setting the following parameters. set enviCLOCK PERIOD) "x" */Openlane/designs/alu/runs/name_of_run/reports/synthesis */Openlane/designs/alu/runs/name_of_run/logs/synthesis Provide the screenshot of GDSII file for designed ALU. Provide synthesis statistics, and STA (setup time and hold time analysis) results. They can be found at the following directories: In the second part, lets change DIE_AREA to 75umx100um and rerun the flow. Provide the GDSII for this run as well. 1. An arithmetic logic unit (ALU) is the center of a central processing unit (CPU). It performers a set of arithmetic and logical micro operations on two input buses at every rising edge of CLK input signal. An active high RST input is used to synchronously reset the output signal Y to logical zeros. The output Y must be available at every rising edge of CLK and the latencies for all functions is 1 cycle. Inputs of ALU: CLK, RST, 8-bit unsigned A, 8-bit unsigned B, 4-bit unsigned SEL Output of ALU: 8-bit unsigned Y Function table of ALU is given below: Function SEL Operation Number ] 2 3 4 5 6 7 8 9 10 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 YA Y<=A+B Y<=A+Bbar YA and B Y<A or B Y<=Axor B Y< Abar Ys=shl A Y<=shr A Y<=0 Go to OpenLane folder Sed -/Openlane Ssudo make mount. Now Openlane docker is started S/flow.tel -design alu-init_design_contig package require openlane 0.9 %prep - design alu %run synthesis Sru_lourplan %run placement Srun_cts The whole functions can be implemented using a single case statement even if it is not an optimal way of doing it. You are free to implement them in your way. You can ignore the carry out in addition operations. run routing Srun magic run_magic_spice_export run magic dre %run lvs run antenna_check. A. (35 Points) Implement the given ALU entity in VHDL language. Provide your VHDL code. (35 Points) Implement the given ALU module in Verilog language. Provide your ende. C. (30 Points) Implement the given ALU using OpenLane Design Flow. Hint: Install OpenLane and Magic tools into your Linux machine as described in the class. Create required design files (alu.v, config.tel and sky130A_sky130_fd_sc_hd_config.tcl) and run the following commands those are also described in the class. Function This command creates an alu folder under /designs folder Copy and modify the design files to this folder same as other example designs flow.tel-interactive Transfer A Addition A plus l's complement of B Logical AND Logical OR Logical XOR Complement A Shift left A Shift right A Transfer 0's Go to this folder Sad -/Openlame/designs/counter/runs/..../results/finishing Run magic Smagic -T sky 130A lef read../../tmp/merged lef def read alu.gds & After completion of flow without any error you can run mugic to see GDSII of your design. Open a new terminal and run the following commands. Make sure nor error is generated throughout the flow. set env(IP SIZING) "absolute" set enviDIE AREA) "0 0 100.0 100.0" In the first part of design, let's make the DIE_AREA is absolute and 100 mx100um and set clock frequency to 200MHz.. You can do it hy setting the following parameters. set enviCLOCK PERIOD) "x" */Openlane/designs/alu/runs/name_of_run/reports/synthesis */Openlane/designs/alu/runs/name_of_run/logs/synthesis Provide the screenshot of GDSII file for designed ALU. Provide synthesis statistics, and STA (setup time and hold time analysis) results. They can be found at the following directories: In the second part, lets change DIE_AREA to 75umx100um and rerun the flow. Provide the GDSII for this run as well.
Expert Answer:
Related Book For
Fundamentals of Physics
ISBN: 978-0471758013
8th Extended edition
Authors: Jearl Walker, Halliday Resnick
Posted Date:
Students also viewed these accounting questions
-
A coin placed 30.0 cm from the center of a rotating horizontal turntable slips when its speed is 50.0 cm/s. (a) What force causes the centripetal acceleration when the coin is stationary relative to...
-
A charge of 170 %C is at the center of a cube of edge 80.0 cm. (a) Find the total flux through each face of the cube. (b) Find the flux through the whole surface of the cube. (c) What If? Would your...
-
A 9.60-C point charge is at the center of a cube with sides of length 0.500 m. (a) What is the electric flux through one of the six faces of the cube? (b) How would your answer to part (a) change if...
-
Sandys Socks makes the worlds best socks. Information for the last eight months follows: Prepare a scatter graph by plotting Sandys data on a graph. Then draw a line that you believe best fits the...
-
Patterson Corporation has four operating divisions. During the first quarter of 2014, the company reported total income from operations of $55,000 and the following results for each division: Further...
-
Describe traditional portfolio management. Give three reasons why traditional portfolio managers like to invest in well-established companies.
-
The variance process in the Heston model satisfy a CIR process: \[d V_{t}=\kappa\left(\bar{V}-V_{t} ight)+\sigma \sqrt{V_{t}} d W_{t}\] Use Ito to calculate the dynamics of the volatility process...
-
La Batre Bicycle Company manufactures commuter bicycles from recycled materials. The following data for July of the current year are available: Quantity of direct labor...
-
Stroud Corporation is an 80%-owned subsidiary of Pennie, Inc., acquired by Pennie several years ago. On January 1, 2017, Pennie sold land with a book value of $60,000 to Stroud for $90,000. Stroud...
-
Following are the income statement and balance sheet for Medtronic PLC. Consolidated Statement of Income, 12 Months Ended ($ millions) April 26, 2019 Net Sales $30,557 Costs and expenses Cost of...
-
4) Storage density of single linked list is (). C. less A. greater than 1 B. equal to 1 than 1 D. not sure
-
The Capability Maturity Model (CMM) was developed by the Software Engineering Institute at Carnegie Mellon and is widely used by both the private and public sectors. What is the purpose of the CMM...
-
List the five maturity levels, and briefly describe each of them.
-
Describe how using a systems development methodology is in line with CMM goals and can help an organization increase its maturity level.
-
Systems development methodology and system life cycle are two terms that are frequently used and just as frequently misused. What is the difference between the two terms?
-
In full cost accounting, when oil and gas are produced jointly, what basis or units of measure are allowed for full cost DD&A? a. Relative energy content only b. Relative revenue only c. Either...
-
1. What are the three basic functional areas of business organizations? Explain the responsibilities of each function in the context of a real (or hypothetical) supply chain firm. 2. List three...
-
Suppose the concentration of glucose inside a cell is 0.1 mm and the cell is suspended in a glucose solution of 0.01 mm. a. What would be the free energy change involved in transporting 10-o mole of...
-
Figure shows cross sections through two large, parallel, non-conducting sheets with identical distributions of positive charge with surface charge density = 1.77 x 10-22C/m2. In unit-vector...
-
Spatial separation between two events for the passing reference frames of Figure events A and B occur with the following space-time coordinates: according to the unprimed frame (xA, tA) and (xB, tB)...
-
Show that a grating made up of alternately transparent and opaque strips of equal width eliminates all the even orders of maxima (except m = 0).
-
Prepare a balanced scorecard for HSBC Bank (http://www.hsbc.com).
-
Starting with Eq. (6.13), which is in conservation form, derive Eq. (6.28), which is in non-conservation form. Equation 6.13: \(\frac{\partial(ho w)}{\partial t}+abla \cdot(ho w...
-
Prepare a balanced scorecard for Mdecins Sans Frontires (http://doctorswithoutborders.org).
Study smarter with the SolutionInn App