1. Write a Verilog module for a 4-bit counter with synchronous reset. Outline code is given...

   

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1. Write a Verilog module for a 4-bit counter with synchronous reset. Outline code is given below module counter_4bit (input clk, reset, output reg [3:0] count) always @ (posedge clk) endmodule; 2. Modify your counter design to include an enable. 3. Now, if you hadn't done so already, implement a counter as a state machine. 1. Write a Verilog module for a 4-bit counter with synchronous reset. Outline code is given below module counter_4bit (input clk, reset, output reg [3:0] count) always @ (posedge clk) endmodule; 2. Modify your counter design to include an enable. 3. Now, if you hadn't done so already, implement a counter as a state machine.

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