1. Write VHDL code to describe the circuit shown below (just write the architecture part including...

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1. Write VHDL code to describe the circuit shown below (just write the architecture part including internal signal declarations; no entity part is needed). E B D D D clk 9 C Y про 2. For each process below, classify the process as combinational or sequential, and draw a circuit schematic. You can use any basic gates, muxes, adders, subtractors, decoders, flip flops/registers, etc. (a) In this module, signal S is a 2-bit std_logic_vector and signals A, B, and Y are 4-bit signed. is process (A, B, S) begin if S= "00 then Y <= A + B; elsif S= "01" then Y <= A - B; elsif S="10" then Y <= B - A; else Y <= "0000"; end if; end process; (b) In this module, all signals are of type std.logic. process (clk) begin if rising edge (clk) then Y <= not Q; Q <P; end if; 1. Write VHDL code to describe the circuit shown below (just write the architecture part including internal signal declarations; no entity part is needed). E B D D D clk 9 C Y про 2. For each process below, classify the process as combinational or sequential, and draw a circuit schematic. You can use any basic gates, muxes, adders, subtractors, decoders, flip flops/registers, etc. (a) In this module, signal S is a 2-bit std_logic_vector and signals A, B, and Y are 4-bit signed. is process (A, B, S) begin if S= "00 then Y <= A + B; elsif S= "01" then Y <= A - B; elsif S="10" then Y <= B - A; else Y <= "0000"; end if; end process; (b) In this module, all signals are of type std.logic. process (clk) begin if rising edge (clk) then Y <= not Q; Q <P; end if;

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