2. Assume the following latencies: PC 5ps I-Mem Add 200ps 70ps 30ps 80ps PC Read address...

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2. Assume the following latencies: PC 5ps I-Mem Add 200ps 70ps 30ps 80ps PC Read address a. If we only need to fetch consecutive instructions what would the cycle time be? b. Given the datapath below what would the cycle time be? Add Mux ALU Regs D-Mem 90ps 220ps Instruction Instruction memory Read register 1 Read register 2 Write register Registers Read data 2 Write data RegWrite data 1 16 Sign- extend to Shift left 2, ALUSrc ALU Add result PCSrc ALU operation Zero ALU ALU M result Address MemWrite MemRead Read data Write Data data memory Sign-Extend 25ps MemtoReg Shift-Left-2 20ps M 2. Assume the following latencies: PC 5ps I-Mem Add 200ps 70ps 30ps 80ps PC Read address a. If we only need to fetch consecutive instructions what would the cycle time be? b. Given the datapath below what would the cycle time be? Add Mux ALU Regs D-Mem 90ps 220ps Instruction Instruction memory Read register 1 Read register 2 Write register Registers Read data 2 Write data RegWrite data 1 16 Sign- extend to Shift left 2, ALUSrc ALU Add result PCSrc ALU operation Zero ALU ALU M result Address MemWrite MemRead Read data Write Data data memory Sign-Extend 25ps MemtoReg Shift-Left-2 20ps M

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Ans Now instructions From data Imem is the fetch Consective instruction Alence ie Critical ... View the full answer