2. Write complete VHDL code to implement the circuit shown below. Use std_logic_vector for the input...

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2. Write complete VHDL code to implement the circuit shown below. Use std_logic_vector for the input w and std_logic for the output z. Your solution should include the code, your do file, and an output for all possible input combinations. do W3 4tol di mux dz dz S, So N 2. Write complete VHDL code to implement the circuit shown below. Use std_logic_vector for the input w and std_logic for the output z. Your solution should include the code, your do file, and an output for all possible input combinations. do W3 4tol di mux dz dz S, So N