3. Convert the following state table to a state diagram. Identify the type of state machine....

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3. Convert the following state table to a state diagram. Identify the type of state machine. Present State Input x 0 1 Output Z A C B 0 B A B 0 C D C 1 D B C 0 Implement a behavioral Verilog model for the state machine in (3). Include a synchronous active high reset input. Assume the state is updated on the positive edge of the clock. 3. Convert the following state table to a state diagram. Identify the type of state machine. Present State Input x 0 1 Output Z A C B 0 B A B 0 C D C 1 D B C 0 Implement a behavioral Verilog model for the state machine in (3). Include a synchronous active high reset input. Assume the state is updated on the positive edge of the clock.