1. (34 pts) In designing an 9-stage instruction-pipelined architecture with forwarding capa- bility, you are asked...

 

Transcribed Image Text:

1. (34 pts) In designing an 9-stage instruction-pipelined architecture with forwarding capa- bility, you are asked to consider the effect on CPI from all possible hazards, assuming that the ideal CPI is 1. • Structural hazards: None • Data hazards: (without compiler's rescheduling) - an instruction of type I immediately followed by another instruction of type IB, and the number of clock cycles stall is 2, an instruction of type I immediately followed by another instruction of type Ic, and the number of clock cycle stall is 1, listed below each is the percentage of occurrence of each combination that will lead to a stall: (an 'x' refers to an instruction of a type other than IA, IB and Ic and a represents 'immediately followed by') 4 (a) IA IB: 10% (b) IA X IB: 5% (c) IA Ic 10% : • Control hazards: (from branch instructions, disregarding those from jump or subrou- tine call instructions) the target address is calculated (PC+ offset) in the 3th stage, the condition is checked (to determine the next PC) in the 6th stage, - an average of 15% of all instructions are branch instructions, among which 70% are 'taken'. (a) (3 pts) What is the increase to CPI from the data hazards? (b) (3 pts) Determine the CPI considering all the hazards, if the pipeline is "frozen" (stalled) until the next PC is known for sure when executing a branch instruction. (c) (3 pts) Repeat (b), if a 'assume-taken' (CPU assumes all branches are taken) approach is used for branch. (d) (3 pts) Repeat (b), if a 'assume-not-taken' (CPU assumes all branches are not-taken) approach is used for branch. (e) (3 pts) In (b), if, without using the pipeline-freezing hardware, a rescheduling compiler is used to find instructions to insert into the 'branch-delay-slots', how many such slots does a compiler have to try to fill after each branch instruction in order to remove all the branch stalls (like the technique we use to fill the 'load-delay-slots' for data hazards), assuming that a nop will be placed into a slot that can not be filled? (f) (3 pts) Repeat (e), if a 'assume-taken' approach is used for branch. (g) (3 pts) Repeat (e), if a 'assume-not-taken' approach is used for branch. (h) (3 pts) In (e), suppose that 80% of all the 'data-hazard-delay-slots' and 60% of all the 'branch-delay-slots' can be filled by the compiler. What is the new CPI? (i) (10 pts) If you are forced to use the 'assume taken' approach, and you are unable to move the condition-checking operation in the pipeline, determine all the stages that you can move the EA calculation operation to so that this approach outperforms the 'assume-not-taken' approach. Show a systematic approach in solving this problem. 1. (34 pts) In designing an 9-stage instruction-pipelined architecture with forwarding capa- bility, you are asked to consider the effect on CPI from all possible hazards, assuming that the ideal CPI is 1. • Structural hazards: None • Data hazards: (without compiler's rescheduling) - an instruction of type I immediately followed by another instruction of type IB, and the number of clock cycles stall is 2, an instruction of type I immediately followed by another instruction of type Ic, and the number of clock cycle stall is 1, listed below each is the percentage of occurrence of each combination that will lead to a stall: (an 'x' refers to an instruction of a type other than IA, IB and Ic and a represents 'immediately followed by') 4 (a) IA IB: 10% (b) IA X IB: 5% (c) IA Ic 10% : • Control hazards: (from branch instructions, disregarding those from jump or subrou- tine call instructions) the target address is calculated (PC+ offset) in the 3th stage, the condition is checked (to determine the next PC) in the 6th stage, - an average of 15% of all instructions are branch instructions, among which 70% are 'taken'. (a) (3 pts) What is the increase to CPI from the data hazards? (b) (3 pts) Determine the CPI considering all the hazards, if the pipeline is "frozen" (stalled) until the next PC is known for sure when executing a branch instruction. (c) (3 pts) Repeat (b), if a 'assume-taken' (CPU assumes all branches are taken) approach is used for branch. (d) (3 pts) Repeat (b), if a 'assume-not-taken' (CPU assumes all branches are not-taken) approach is used for branch. (e) (3 pts) In (b), if, without using the pipeline-freezing hardware, a rescheduling compiler is used to find instructions to insert into the 'branch-delay-slots', how many such slots does a compiler have to try to fill after each branch instruction in order to remove all the branch stalls (like the technique we use to fill the 'load-delay-slots' for data hazards), assuming that a nop will be placed into a slot that can not be filled? (f) (3 pts) Repeat (e), if a 'assume-taken' approach is used for branch. (g) (3 pts) Repeat (e), if a 'assume-not-taken' approach is used for branch. (h) (3 pts) In (e), suppose that 80% of all the 'data-hazard-delay-slots' and 60% of all the 'branch-delay-slots' can be filled by the compiler. What is the new CPI? (i) (10 pts) If you are forced to use the 'assume taken' approach, and you are unable to move the condition-checking operation in the pipeline, determine all the stages that you can move the EA calculation operation to so that this approach outperforms the 'assume-not-taken' approach. Show a systematic approach in solving this problem.

Answer rating: 100% (QA)

a The increase to CPI from data hazards is 3 This is because there are 3 data hazard stalls per 100 instructions b The CPI with all hazards considered ... View the full answer