5.2 Rewrite the following CISC-style program fragment so that it executes correctly on a RISC (load-store)...

 

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5.2 Rewrite the following CISC-style program fragment so that it executes correctly on a RISC (load-store) processor that executes the GPR ISA outlined in the previous chapter. Assume that the GPR ISA provides only the register addressing mode, and that there are enough registers in the processor to hold any temporary values that you need to generate. ADD r3, (r1), (r2) SUB r4, r3, (r5) MUL (r6), r7, r4 5.2 Rewrite the following CISC-style program fragment so that it executes correctly on a RISC (load-store) processor that executes the GPR ISA outlined in the previous chapter. Assume that the GPR ISA provides only the register addressing mode, and that there are enough registers in the processor to hold any temporary values that you need to generate. ADD r3, (r1), (r2) SUB r4, r3, (r5) MUL (r6), r7, r4

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Example suppose these are the value for the below operations And r1r2r3r4r5r5r6r7 are register to st... View the full answer