7.33 A RISC processor executes the following code. There are no data dependencies. r0, r1, r2...

  

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7.33 A RISC processor executes the following code. There are no data dependencies. r0, r1, r2 ADD ADD r3, 14, 15 ADD 16, 17, 18 ADD r9, r10, r11 ADD r12, r13, r14 ADD r15, r16, r17 a. Assuming a four-stage pipeline (fetch, operand fetch, execute, and write) what registers are being read during the sixth clock cycle and what register is being written? b. Assuming a five-stage pipeline (fetch, operand fetch, execute, write, and store) what registers are being read in the sixth clock cycle and what register is being written? 7.33 A RISC processor executes the following code. There are no data dependencies. r0, r1, r2 ADD ADD r3, 14, 15 ADD 16, 17, 18 ADD r9, r10, r11 ADD r12, r13, r14 ADD r15, r16, r17 a. Assuming a four-stage pipeline (fetch, operand fetch, execute, and write) what registers are being read during the sixth clock cycle and what register is being written? b. Assuming a five-stage pipeline (fetch, operand fetch, execute, write, and store) what registers are being read in the sixth clock cycle and what register is being written?

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a In a fourstage pipeline each stage takes one clock cycle to complete Given the instructions provid... View the full answer