A computer system contains a main memory of 32KB. It also has a 4KB cache divided into four-lines/set with 64B per line. Assume that the cache is initially empty. The processor fetches words from locations 0, 1, 2, . . ., 4351 in that order. It then repeats this fetch sequence nine more times. The cache is 10 times faster than main memory. Estimate the improvement resulting from the use of the cache. Assume an LRU policy for block replacement. Show the state of cache at the end.

Consider the following assembly code:

Instruction	Description
LD R1, 45(R2)	Read data from memory and store in R1. Memory address is calculated by adding 45 to the content of R5
ADD R7, R1, R5	Add contents of R1 and R5 and store to R7
SUB R8, R1, R7	Subtract content of R7 from content of R1 and save to R8
XOR R7, R8, R8	Logical Ex-OR between contents of R1 & R1. Store result to R9
BEZ R7, Target	Jump to Target if R7 is Zero
LD R5, 50(R2)	Read data from memory and store in R5. Memory address is calculated by adding 50 to the content of R2
LD R8, 45(R2)	Read data from memory and store in R8. Memory address is calculated by adding 45 to the content of R2
ADD R10, R8, R5	Add contents of R8 and R5 and store to R10
Target: AND R2, R3, R4	Logical AND between contents of R3 & R4. Store result to R2
ADD R10, R8, R2	Add contents of R2 and R8 and store to R10
END

a) Use five-stage pipeline containing fetch, decode, memory read, execute, write-back units, show the execution of above instructions. Data dependencies and control hazards, if detected must be resolved by stalling the pipeline as required. Assume that a multi-port RAM is used with the CPU running at 1GHz. Calculate the execution time and compare time that would have required in a non-pipelined processor to run the same program.