Assembly Language Bitwise And, OR, XOR, & Shift

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Assume the following values are stored at the indicated memory addresses and registers: Address Value Register Value 0x500 0x983FODFD Seax 0x500 0x504 0xC995769D sebx 0xA6DC437 0x508 0x8F9D82FE secx OxEF8B5502 0x50C 0xC78E3EFF sedx In the table below, show only the new value of the destination in hexadecimal. For example, if the instruction is andbal, ah, you should show the value of register ah after the instruction executes. Note: From the Intel manual about shifts 1. 2. 3. 4. 5. 6. 7. 8. 9. The destination operand can be a register or a memory location. The count operand can be an immediate value or the CL register. The count is masked to 5 bits. The count range is limited to 0 to 31. Instruction andb%cl, %bl andb 10 (%eax), %cl orb ch, dh orb 9 (seax), %d1 OxA049E577 xorb %bh, %bl xorb 6 (%eax), %bh shrl $8, 4 (%eax) sarl %cl, %edx sarl %cl, %ebx 10. salb $2, %bh 11. shll cl, %ebx New Value (in hex) Assume the following values are stored at the indicated memory addresses and registers: Address Value Register Value 0x500 0x983FODFD Seax 0x500 0x504 0xC995769D sebx 0xA6DC437 0x508 0x8F9D82FE secx OxEF8B5502 0x50C 0xC78E3EFF sedx In the table below, show only the new value of the destination in hexadecimal. For example, if the instruction is andbal, ah, you should show the value of register ah after the instruction executes. Note: From the Intel manual about shifts 1. 2. 3. 4. 5. 6. 7. 8. 9. The destination operand can be a register or a memory location. The count operand can be an immediate value or the CL register. The count is masked to 5 bits. The count range is limited to 0 to 31. Instruction andb%cl, %bl andb 10 (%eax), %cl orb ch, dh orb 9 (seax), %d1 OxA049E577 xorb %bh, %bl xorb 6 (%eax), %bh shrl $8, 4 (%eax) sarl %cl, %edx sarl %cl, %ebx 10. salb $2, %bh 11. shll cl, %ebx New Value (in hex)

Answer rating: 100% (QA)

Instruction New Value in hex andb cl bl 0x4 andb 10 eax cl 0x2 orb ch dh 0x9D orb 9 eax dl 0xDD xorb bh bl 0x0 xorb 6 eax bh 0x0 shrl 8 4 eax 0x98 sar... View the full answer