B.49 Assume that a gate array contains the type of logic cell depicted in Figure PB.9....

   

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B.49 Assume that a gate array contains the type of logic cell depicted in Figure PB.9. The inputs in₁,..., in can be connected to either 1 or 0, or to any logic signal. (a) Show how the logic cell can be used to realize f = x1x2 + x3. (b) Show how the logic cell can be used to realize f = x₁x3 + x2X3. T in1 in2 in 3 dou mo 20 in4 in5 in6 1916 Figure PB.9 ut at wod wodz 88.8 out Sugit in7 ghizo 2011 mole A gate-array logic cell. da PE.8 yad 5.0/0.5 VA.co (A.S B.49 Assume that a gate array contains the type of logic cell depicted in Figure PB.9. The inputs in₁,..., in can be connected to either 1 or 0, or to any logic signal. (a) Show how the logic cell can be used to realize f = x1x2 + x3. (b) Show how the logic cell can be used to realize f = x₁x3 + x2X3. T in1 in2 in 3 dou mo 20 in4 in5 in6 1916 Figure PB.9 ut at wod wodz 88.8 out Sugit in7 ghizo 2011 mole A gate-array logic cell. da PE.8 yad 5.0/0.5 VA.co (A.S B.49 Assume that a gate array contains the type of logic cell depicted in Figure PB.9. The inputs in₁,..., in can be connected to either 1 or 0, or to any logic signal. (a) Show how the logic cell can be used to realize f = x1x2 + x3. (b) Show how the logic cell can be used to realize f = x₁x3 + x2X3. T in1 in2 in 3 dou mo 20 in4 in5 in6 1916 Figure PB.9 ut at wod wodz 88.8 out Sugit in7 ghizo 2011 mole A gate-array logic cell. da PE.8 yad 5.0/0.5 VA.co (A.S B.49 Assume that a gate array contains the type of logic cell depicted in Figure PB.9. The inputs in₁,..., in can be connected to either 1 or 0, or to any logic signal. (a) Show how the logic cell can be used to realize f = x1x2 + x3. (b) Show how the logic cell can be used to realize f = x₁x3 + x2X3. T in1 in2 in 3 dou mo 20 in4 in5 in6 1916 Figure PB.9 ut at wod wodz 88.8 out Sugit in7 ghizo 2011 mole A gate-array logic cell. da PE.8 yad 5.0/0.5 VA.co (A.S