Change the asynchronous-clear-circuit of the figure to the synchronous-clear-circuit, The modified register will have parallel load capability and asynchronous clear capability, but no asynchronous clear circuit. The register is cleared synchronously when the clock pulse in the  CP goes through a negative transition provided R = 1 and S = 0 in all the flip-flops.

Transcribed Image Text:

Load R S Q R 13 R СР Clear Load R S Q R 13 R СР Clear