Consider the following Piplined MIPS code: addi $13, $10, 12 lw $12, 4(50) add $11, $13,...

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Consider the following Piplined MIPS code: addi $13, $10, 12 lw $12, 4(50) add $11, $13, $12 sub $12, $13, $11 sw $t2, 8($0) a) Label all dependences within one iteration of this code b) The above code produces the pipeline diagram shown below when run on a 5-stage MIPS pipeline with stages IF (fetch), ID (decode). EX (execute), MEM (memory) and WB (write-back). complete the table bellow in order to calculate the number of clock cycle to excute the code. Instruction 1 2 4 5 7 9 10 11 12 13 14 IF MEM WB sub w addi add Sw ID 3 EX 15 Consider the following Piplined MIPS code: addi $13, $10, 12 lw $12, 4(50) add $11, $13, $12 sub $12, $13, $11 sw $t2, 8($0) a) Label all dependences within one iteration of this code b) The above code produces the pipeline diagram shown below when run on a 5-stage MIPS pipeline with stages IF (fetch), ID (decode). EX (execute), MEM (memory) and WB (write-back). complete the table bellow in order to calculate the number of clock cycle to excute the code. Instruction 1 2 4 5 7 9 10 11 12 13 14 IF MEM WB sub w addi add Sw ID 3 EX 15

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a Labeling Dependencies RAW Read After Write Dependencies add 11 13 t2 depends on addi 13 10 12 reads 13 sub 12 13 t1 depends on addi 13 10 12 reads 1... View the full answer