Consider the following sequence of instructions, and assume that it is executed on a 5-stage pipelined...

  

Transcribed Image Text:

Consider the following sequence of instructions, and assume that it is executed on a 5-stage pipelined data path (IF, D/R, ALU, DM, RW). Also assume that writing into a register happens in the first half of the clock cycle while reading from a register happens in the second half of the clock cycle: lw $55,0($s4) add $s7, $s5, $s5 sub $s1, $s5, $s2 sw $s1, 0($s4) #11 #12 #13 #14 a. Assume the 5-stage MIPS pipeline with no forwarding, what is the total number of stall cycles? What is the execution time (in cycles) for the whole program? Sketch a diagram to explain your answer. b. Assume the 5-stage MIPS pipeline with full forwarding, what is the total number of stall cycles? What is the execution time (in cycles) for the whole program? Sketch a diagram to explain your answer. Consider the following sequence of instructions, and assume that it is executed on a 5-stage pipelined data path (IF, D/R, ALU, DM, RW). Also assume that writing into a register happens in the first half of the clock cycle while reading from a register happens in the second half of the clock cycle: lw $55,0($s4) add $s7, $s5, $s5 sub $s1, $s5, $s2 sw $s1, 0($s4) #11 #12 #13 #14 a. Assume the 5-stage MIPS pipeline with no forwarding, what is the total number of stall cycles? What is the execution time (in cycles) for the whole program? Sketch a diagram to explain your answer. b. Assume the 5-stage MIPS pipeline with full forwarding, what is the total number of stall cycles? What is the execution time (in cycles) for the whole program? Sketch a diagram to explain your answer.