Consider the following sequence of instructions executing on a 5-stage MIPS pipeline with full hazard detection...
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Consider the following sequence of instructions executing on a 5-stage MIPS pipeline with full hazard detection and forwarding support, with branch resolution in D: In what cycles will instructions 3 and 5, respectively, complete (Writeback, even if nothing occurs in W)? 0 1 2 3 4 5 6 7 CYCLE 1: LW $1, 1D0C($0) F DE MW 2: LW $2,0($1) F 3: SW $3, 4($2) 4: LW $1,0($2) 5: BEQ $1, $0, FOO 8,12 6,8 7,11 10,8 Consider the following sequence of instructions executing on a 5-stage MIPS pipeline with full hazard detection and forwarding support, with branch resolution in D: In what cycles will instructions 3 and 5, respectively, complete (Writeback, even if nothing occurs in W)? 0 1 2 3 4 5 6 7 CYCLE 1: LW $1, 1D0C($0) F DE MW 2: LW $2,0($1) F 3: SW $3, 4($2) 4: LW $1,0($2) 5: BEQ $1, $0, FOO 8,12 6,8 7,11 10,8
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Related Book For
Computer Organization and Design The Hardware Software Interface
ISBN: 978-0124077263
5th edition
Authors: David A. Patterson, John L. Hennessy
Posted Date:
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