Create a Verilog HDL Data flow model for the 16-bit magnitude comparator shown below. .FO will...

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Create a Verilog HDL Data flow model for the 16-bit magnitude comparator shown below. .FO will be 1 if X is equal to Y otherwise it will be zero. .F1 will be 1 if X is less than Y otherwise it will be zero. F2 will be 1 if X is greater than Y otherwise it will be zero. 16 X Y 16 FO 16-bit magnitude comparator F1 F2 Create a Verilog HDL Data flow model for the 16-bit magnitude comparator shown below. .FO will be 1 if X is equal to Y otherwise it will be zero. .F1 will be 1 if X is less than Y otherwise it will be zero. F2 will be 1 if X is greater than Y otherwise it will be zero. 16 X Y 16 FO 16-bit magnitude comparator F1 F2